Field of the Invention
The present invention relates to a method for automatically generating a netlist of an FPGA (Field Programmable Gate Array) program.
Description of the Background Art
In the conventional art, an FPGA program is compiled in an abstract development environment. This permits the users to develop an FPGA program even without detailed knowledge about FPGAs and tool flows. One example of such a development environment is the program “Simulink” by the company The Mathworks in connection with the program “System Generator for DSP” by the company Xilinx. A model of the FPGA program is produced in such a development environment. Testing the model that has been produced requires a build of a netlist for the configuration of an FPGA based on the model of the FPGA program. Typically, an FPGA build includes the steps of synthesis, placement, and routing. The netlist that has been prepared in this way is then used to produce a bit stream for the configuration of the FPGA. The process of the build, however, lasts for a comparatively long time so that when there are frequent changes to the model of the FPGA program, this results in long wait times.
In other words, to define the behavior of the FPGA, the user provides a hardware description language (HDL) or a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. However, schematic entry can allow for easier visualisation of a design. Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA. This file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM.
In order to reduce the time required until a completely placed and routed netlist is available after completion of the modeling, it is known to manually divide the model into components, to manually partition an FPGA, to synthesize each of the components individually, and to place and route them appropriately for a partition. During the complete build for the whole model, the already placed and routed netlists of the components are simply accepted unchanged and the connections between the components are produced as needed. This approach can be implemented using the tool flow that Xilinx refers to as “hierarchical tool flow.” The partitioning of an FPGA is also referred to as floor-planning.
U.S. Pat. No. 8,407,645, which is incorporated herein by reference, discloses the division of a model and the separate building of individual components.